1. Field of the Invention
The present invention relates to a memory device, and in particular, to a power down circuit for a memory device.
2. Background of the Related Art
Burn-in mode is performed on a memory device to eliminate premature failures after fabricating a substrate and packaging the memory device regardless of an auto power down function. In the burn-in mode, a high voltage is applied to operate memory cells and neighboring circuits, and thereby, a vulnerable memory device can be eliminated.
In a static random access memory device (SRAM), a direct current (DC) voltage keeps flowing through power source supplying elements during a read cycle and a write cycle in a burn-in mode as well as in a normal mode, which results in a high power consumption in the SRAM. However, reducing power consumption in the SRAM is desirable.
U.S. Pat. No. 4,962,487 (issued: Oct. 9, 1990) discloses a method for reducing power consumption during a write cycle, which was proposed to satisfy the demand for lower SRAM power consumption. In U.S. Pat. No. 4,962,487, the cycle for performing an actual write operation is not determined using a write cycle determined by an external control signal, but by a cycle during which a pulse signal generator generates an arbitrary pulse signal. Therefore, when an actual write cycle is finished, the mode is converted into a power down mode even during a write cycle according to the pulse signal generator.
U.S. Pat. No. 4,947,379 (issued: Aug. 7, 1990) discloses data output circuits connected to word lines and bit lines that are disabled after a word line enabling pulse signal and a sense amplifier enabling pulse signal are finished. Thereby, power consumption during the read cycle can be reduced.
FIG. 1 is a block diagram showing a related art power down circuit. As shown in FIG. 1, a power down timer 15 receives a plurality of address transition detecting signal (.0.ATD1 . . . .0.ATDk) from an address transition detector 5, a chip select detecting signal (.0.CSD) and a write mode detecting signal (.0.WTD) from a chip select/write mode detector 13 and a plurality of data input detecting signals (.0.DTD1 . . . .0.DTDn) from a data transition detector 33, to generate a power down signal (.0.PD) having an arbitrary pulse width.
FIG. 2 is a circuit diagram showing the power down timer 15. As shown in FIG. 2, the power down timer 15 receives the address transition detecting signals (.0.ATD1 . . . .0.ATDk), the data input detecting signals (.0.DTD1 . . . .0.DTDn), the chip select detecting signal (.0.CSD) and the write mode detecting signal (.0.WTD), respectively, through NOR gates 42,44,46. A NAND gate 48 receives the output signals from the NOR gates 42,44,46. An output signal from the NAND gate 48 is inputted to a pulse extending circuit 50, from which the power down signal (.0.PD) is generated in response to any transition among the detecting signals.
As shown in FIG. 1, the power down signal (.0.PD) controls a data input circuit 29 and is inputted to a plurality of NOR gates (NOR1 . . . NORn) to enable a plurality of word lines (WL1 . . . WLn). The power down signal (.0.PD) is also inputted to a NOR gate 17 to enable a write switching signal (.0.SWE) for connecting the data input circuit 29 to a pair of data lines (DL,DLB). The power down signal is also inputted to a NOR gate 31 to generate a sense amplifier enabling signal (.0.SAE).
With reference to the timing waveform diagrams shown in FIG. 3, the read and write operations of the circuit in FIG. 1 will now be described. During a write cycle, a chip select signal (.0.CSB) and a write enabling signal (WEB) are maintained low level, as shown in FIGS. 3A and 3C. In addition, an output enabling signal (OEB) is maintained high level as shown in FIG. 3D.
First, when a write cycle starts, the chip select detecting signal (CSD) is outputted as a high pulse signal as shown in FIG. 3F in response to a level transition of the chip select signal (.0.CSB). Further, the address transition detecting signals (.0.ATDi:i=1 . . . k) are outputted as a high pulse signal as shown in FIG. 3H in response to a transition of address bits (Ai:i=1 . . . k) as shown in FIG. 3B.
The write mode detecting signal (.0.WTD) is outputted as a high pulse signal, as shown in FIG. 3G, in response to a transition to a low level of the write enabling signal (WEB). The data detecting signals (.0.DTDi:i=1 . . . n) are outputted as a high pulse signal shown in FIG. 3I, in response to a transition of an input data bit. Accordingly, the power down signal (.0.PD) shown in FIG. 3J is generated from the power down timer 15 in accordance with a logical state of the above-mentioned detecting signals (.0.CSD, .0.WTD, .0.ATDi and .0.DTDi).
While the power down signal (.0.PD) is maintained low level with a predetermined pulse width by the pulse extending circuit 50, the selected word lines (WLi:i=1 . . . n) are enabled. Then, when the power down signal (.0.PD) becomes a high level, the enabling operation for the word line (WLi) is finished. Accordingly, the data input circuit 29 is disabled and the write switching signal (.0.SWE) becomes low level as shown in FIG. 3N. As a result, current is inhibited from flowing from the data input circuit 29 to the memory cells.
During the read cycle, the chip select signal (.0.CSB), the write enabling signal (WEB) and the output enabling signal (OEB) are maintained low, high and low levels, respectively, as shown in FIGS. 3A, 3C and 3D. In accordance with the power down signal (PD) maintained low level as shown in FIG. 3J, the sense amplifier enabling signal (.0.SAE) is outputted as a high pulse signal as shown in FIG. 3O during the cycle of the predetermined pulse width of the power down signal (PD). Then, the selected word line (WLi) and the sense amplifier 35 are disabled after a latching operation by the data output buffer 37 when the power down signal (PD) is transited to be high level. That is, the circuit in FIG. 1 disables a word line in a burn-in mode after a data writing into the memory cells is performed during the write cycle and disables the word line and the sense amplifier after a data reading from the memory cells is performed during the read cycle. Thereby, the current path is cut off, which reduces the power consumption.
However, the related art power down circuit has various disadvantages. When a burn-in is performed to eliminate premature failures irrespective of a power down function after the memory device is packaged or a wafer is produced, a high voltage is applied to a memory cell as shown in FIG. 4 and to peripheral circuits for the operation thereof, thereby to prevent a vulnerability in a semiconductor device. In particular, the burn-in eliminates defects in a gate oxide of a transistor. However, in related art memory devices having an auto power down function, burning-in proceeds only during a relatively short period when powering-down does not occur. Thus, a burn-in effect influences only part of the memory cells and peripheral circuits, and as a whole, the burn-in effect is reduced.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.